Power Electronic Tips https://www.powerelectronictips.com/category/featured-tutorials/ Power Electronic News, Editorial, Video and Resources Tue, 05 Nov 2024 19:24:34 +0000 en-US hourly 1 https://wordpress.org/?v=6.7 https://www.powerelectronictips.com/wp-content/uploads/2016/11/cropped-favicon-512x512-32x32.png Power Electronic Tips https://www.powerelectronictips.com/category/featured-tutorials/ 32 32 Mitigate reverse recovery overshoot in MOSFET body diodes https://www.powerelectronictips.com/mitigate-reverse-recovery-overshoot-in-mosfet-body-diode/ https://www.powerelectronictips.com/mitigate-reverse-recovery-overshoot-in-mosfet-body-diode/#respond Wed, 06 Nov 2024 10:21:01 +0000 https://www.powerelectronictips.com/?p=23504 Because of their compact size, higher efficiency, and superior performance in high-power applications, SiC MOSFETs are now replacing Si devices in switching applications. SiC devices enable faster switching times, significantly reducing switching losses. These advantages stem from the unique electrical and material properties of SiC-based devices — snappy reverse recovery inherent to the structure of […]

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Because of their compact size, higher efficiency, and superior performance in high-power applications, SiC MOSFETs are now replacing Si devices in switching applications. SiC devices enable faster switching times, significantly reducing switching losses. These advantages stem from the unique electrical and material properties of SiC-based devices — snappy reverse recovery inherent to the structure of the MOSFET body diode, which tempers SiC MOSFET benefits. During a snappy reverse recovery event, devices can experience large voltage spikes, posing risks to both the device and the overall system. Additional design challenges include increased electromagnetic interference (EMI) and unintended faults, such as false gate events or parasitic turn-on [3] [4]. Fortunately, you can mitigate these effects, which optimizes system performance.

Reverse recovery at the system Level:

A SiC MOSFET integrated with a soft-body diode increases a converter circuit’s operating frequency and efficiency while decreasing the number of components.

Figure 1 shows a full bridge topology of a single-phase two-level converter and a pulse pattern that will cause a reverse recovery event. At t0, all switches start in the off state. S1 and S4 are initially turned on during t1, letting the current pass through the load. During t2, S4 returns to the off-state. The current must then change to the freewheeling path, which utilizes the body diode in S2. This time is known as dead time, and the current will decay due to the path resistance. During the transition period between t2 and t3, S4 turns back on, causing a shoot-through scenario that forces the body diode of S2 to undergo reverse recovery. After the recovery instant, the parasitic inductance in the current path results in a voltage overshoot to maintain the current in the path.

Figure 1. The schematic of a single-phase, two-level converter shows the path of the freewheeling current (blue arrow) prior to the reverse recovery event. The pulse pattern shows the freewheeling path and reverse recovery event.

Reverse recovery and softness factor

A snappy or reverse recovery occurs when a SiC diode transitions from “forward-conduction” to an “off-state.” To simplify the reverse recovery event, Figure 2 shows a diode’s ideal recovery current and voltage waveform (Fig. 2a) and a non-ideal current waveform for a MOSFET (Fig. 2b).

Figure 2. This comparison of (a) the ideal reverse recovery current (solid line) and voltage (dashed line) of a diode and (b) a measured MOSFET body diode current recovery waveform shows that the measured waveform contains ringing caused by parasitic inductance in the circuit.

Fig. 2a shows two regions of time based on Idiode. From t0 to t1, the reverse voltage VR (dashed line) application forces the current to drop at a constant rate, dI/dt. During this period, the rate at which dI/dt changes is determined mainly by the applied VR, circuit elements such as the complementary device’s external RG, and parasitic circuit inductance. At the start of t1, excess carriers are removed from the drift region, and a depletion region begins to form, which builds the voltage across the diode. The voltage reaches its target value VR when Irrm is met at t2, and there is no additional bias from the voltage source VR that increases the current magnitude further. From t2 to t3, the voltage overshoots its target value as the parasitic inductance opposes the decreasing loop current, eventually settling at VR. The voltage overshoot peak depends on the circuit’s parasitic inductance and rate of change of recovery current dIr/dt(max).

Typically, we use two formulas to evaluate the softness factor of a recovery event. Below is S1, a single-parameter ratio:

where ta = t– t1 and tb = t3 – t2.

When S1 = 1, the time it takes for the current to reach Irrm equals the time it takes to return to 0 A or leakage values.

A second method of measuring the softness of a reverse recovery event is defined in the equation below:

Where: dI/dt is the current at the initial zero-crossing of the commuting current, and dIr/dt(max) is the max return current during tb.

When S2 = 1, the current flow rate into and out of the body diode is equivalent. Most devices never achieve an ideal S1 and S2 value. A snappy recovery will occur when S1 and S2 are less than 1, while a value greater than 1 is considered a soft recovery.

Figure 3 shows a half-bridge test circuit used to perform reverse recovery characterization. Like the pulse pattern described in Figure 1, the high-side device will initially switch on and off to allow a controlled amount of current to conduct through the body diode of the low-side MOSFET. The high-side device then turns back on, forcing the freewheeling current to commutate, overshoot, and eventually settle, completing the reverse recovery event. Test boards and other external circuitry should limit the influence on body diode characterization. Do your best to minimize the test board’s stray inductance in accordance with good PCB layout practice and ensure that the external circuitry is not limiting the switching capabilities of the MOSFET. Minimizing the area of the power and gate loops will reduce inductance and achieve greater switching control.

Figure 3. This test circuit of a half-bridge configuration lets you characterize reverse recovery parameters in a MOSFET

Managing reverse recovery and EMI

Temperature dependence is the major factor for VDS overshoot and peak IDS values during the reverse recovery event. Tests performed at high temperatures will provide “worst-case scenario” results. The free-wheeling current through the body diode slowly dissipates over time as heat. This heat causes a temperature change in the junction, decreasing the conductive path’s resistance and thus increasing the initial dI/dt.

Figure 4a shows the temperature dependence of the reverse recovery current. The test parameters include an RG(ext) = 5 Ω, VDS = 800 V, and ID = 40 A. Increasing external gate resistance is recommended to achieve softer recovery characteristics such as reduced Qrr, Irrm, and dampened ringing. Improvements in reverse recovery obtained from increasing RG(ext) are shown in Figure 4b). Higher gate resistance reduces the risk of snappy reverse recovery and can increase switching losses due to increased trr if overly dampened. Figure 4b) shows the reverse recovery current plotted versus time for various external RG values. The reduced ringing effect in the current waveform will reduce unwanted EMI.

body diodes
Figure 4. ID vs. t (a) at 25°C and 175°C and (b) for various RG(ext) values shows the effects of temperature and external gate resistance on reverse recovery.

Table 1 demonstrates that increasing RG will decrease dI/dt and Qrr and dampen the initial oscillatory peak current level. In contrast, increasing RG also increases trr, creating a tradeoff between overshoot and switching times. Always visually inspect the waveform  after measuring it.

body diodes
Table 1. Reverse diode characteristics for various RG(ext) values.

Impact of reverse recovery on voltage and energy

You must also consider reverse recovery effects on voltage to ensure a power circuit won’t exceed the device’s safe operating area (SOA). Parasitic inductance in the commutating current path causes an overshoot in the voltage waveform. If ignored, you will violate SOAs and reduce the system efficiency and lifetime of the semiconductor device.

Figure 5a shows the ISD recovery waveform of the low-side device as a function of time at T = 125°C and VDS = 800 V. Figure 5b shows the VDS recovery waveform as a function of time and Figure 5c shows the peak VDS value as a function of external gate resistance. The devices tested are in a half-bridge configuration with 4 dies in parallel per switch position. As expected, the VDS peak decreases as RG(ext) increases. An RG(ext) >3 Ω is required to remain within the device’s SOA.

body diodes
Figure 5. Shows the (a) IDS vs t (b) VDS vs t (c) and VDS peak vs. RG(ext) results using four die in parallel in a half-bridge configuration. Peak VDS can be easily managed by increasing the external gate resistance to a module.

Conclusion

The circuits shown help you mitigate overshoot voltage and unwanted EMI during the reverse recovery of a SiC MOSFET body diode. Reverse recovery is an inherent occurrence in MOSFET body diodes, and negative effects are amplified by increased junction temperature. Board or module circuit parasitics create oscillatory voltage spikes that can break device SOA limitations. You should accurately characterize the softness factor of a MOSFET body diode to understand the benefits gained from mitigation techniques fully. Increasing external gate resistance is the most common method for softening recovery characteristics and managing VDS overshoot.

References

1993. J. B. Mohit Bhatnagar, “Comparison of 6H-SiC, 3C-SiC, and Si for Power Devices,” IEEE Transactions on Electronic Devices, vol. 40, no. 3, pp. 645-655, 1993.Singh R., S. Ryu, J.W. Palmour, A.R. Hefner. J. Lai, “1500 V, 4 Amp 4H-Sic JBS Diodes,” in International Symposium on Power Semiconductor Devices, Toulouse, 2000.
Romero, A., “Capacitance Ratio and Parasitic Turn-on,” Wolfspeed Inc., Durham, 2023.
Yuan, X., S. Walder and N. Oswald, “EMI Generation Characteristics of SiC and Si Diodes: Influence of Reverse-Recovery Characteristics,” IEEE Transactions of Power Electronics, vol. 30, no. 3, pp. 1131-1136, 2015.

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Bipolar junction transistors show their muscle https://www.powerelectronictips.com/bipolar-junction-transistors-show-their-muscle/ https://www.powerelectronictips.com/bipolar-junction-transistors-show-their-muscle/#comments Wed, 23 Oct 2024 09:43:03 +0000 https://www.powerelectronictips.com/?p=23465 Recent enhancements to the classic BJT show that the classic transistor has plenty of life left and can challenge SiC and GaN devices in some power applications. Amidst the advances in CMOS and wide bandgap semiconductor technology, you can easily forget that the first transistor invented by William Shockley in 1949 was a bipolar junction […]

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Recent enhancements to the classic BJT show that the classic transistor has plenty of life left and can challenge SiC and GaN devices in some power applications.

Amidst the advances in CMOS and wide bandgap semiconductor technology, you can easily forget that the first transistor invented by William Shockley in 1949 was a bipolar junction transistor (BJT). Even though they have fallen out of vogue, these humble devices continue to function efficiently and reliably in huge volumes within various types of electronic equipment. Indeed, in some applications, BJTs can outperform their more illustrious CMOS counterparts. Recent enhancements in BJT technology will keep them an important part of the semiconductor technology landscape.

Low saturation voltage

Some inherent disadvantages of BJTs compared to MOSFETs include their requirement for a continuous base current and a higher saturation voltage across the collector-emitter terminals. The high current gain (hFE) and low saturation voltage (VCEsat) of “low VCEsat” BJTs, however, reduce the base current drive and power dissipation, thereby making them a viable alternative to MOSFETs in the following applications.

Load-switch

A common version of the load switch, where the load is ground-connected, and the positive supply voltage is turned on and off, is shown in Figure 1. Reverse currents from the output to the input are blocked by the inherent feature of the BJT. This is an important feature if you use a load switch in a charger application; for example, a battery connected to the output terminal must not feed current into the input power supply when switched off. If the load transistor is a p-channel MOSFET (instead of a BJT), the body diode could conduct a reverse current to prevent this from happening. You would need an extra diode or a second FET, which adds additional cost. Because the diode’s forward voltage adds to the FET’s RDSon losses, the efficiency of this type of load switch is reduced.

Figure 1. Typical load-switch circuit uses a low VCEsat PNP BJT in the load path (T1) and a general-purpose control transistor (T2).

Another advantage of using a BJT is that it only requires a small control voltage. BJT’s base-emitter diode forward voltage is approximately 0.7 V with only a small spread. On the other hand, the gate-source threshold of a MOSFET can have a wider spread of values. That means you need a larger control voltage.

To be fully turned on, a MOSFET must also apply a higher drive voltage than the gate-source threshold. If you need to switch small voltages, then a p-channel MOSFET could create issues in the load path. Yet another advantage of using a low VCEsat BJT in this application is its superior ESD robustness.

Low-voltage dropout regulator

Within the family of linear regulators exists a subgroup called low-voltage dropout regulators (LDOs). While standard linear regulators based on an NPN BJT require headroom between their input and output voltage of at least VCEsat + VBE, the only headroom required by an LDO realized with a PNP BJT is VCEsat. Using a low VCEsat BJT helps to keep this headroom very small. Figure 2 (a) shows an LDO using an NPN BJT in the load path, while Figure 2 (b) uses a PNP BJT. These linear regulators are optimal for battery-powered applications because of their high efficiency. The high forward gain of low VCEsat BJTs increases efficiency because they need low driving currents.

Figure 2. These LDO examples show how to use (a) low VCEsat NPN-BJT and (b) VCEsat PNP-BJT as pass transistors.

Device matching is still relevant

In many electronic circuits, the exact values of BJT device parameters are not especially important if they lie within a specified range. Many applications, however, require BJTs whose parameters closely match each other. While many semiconductor manufacturers offer individual BJTs whose parameters have tight tolerances, these may still not provide the necessary level of matching, especially as the operating temperature of an application increases. You may, therefore, need matched pairs.

Current mirror for biasing

Like that shown in Figure 3, the current mirror circuit is commonly used as a current source to ‘bias’ (set the operating point) other application circuits like amplifiers or comparators. Assuming that both transistors are identical and R1 = R2, IOUT will exactly replicate IIN. This is expressed mathematically as:

Figure 3. This current-mirror circuit uses discrete BJTs Q1 and Q2.

For a perfectly matched pair, the ratio between the selected values for R1 and R2 sets the value of k1. IOUT should also track IIN across the input current values required by design. However, slight differences in the physical characteristics of the BJTs can cause an unwanted deviation, thereby making it more difficult to precisely define the behavior of the application that the mirror circuit is biasing.

Current sensing

Newer applications such as electric vehicles (EVs) or mild-hybrid vehicles (HEVs) require that load current drawn from a battery be sensed close to the battery. The sensing current must be converted to a voltage within the input range of an analog-to-digital converter (ADC) or a microcontroller (MCU). Thus, it must be small, and the voltage must be provided relative to the ground. This can be done using a current sensing circuit, as shown in Figure 4, where V1 represents the 48 V battery voltage and I1 is the load current drawn from it. This circuit is based on two current mirrors – one pair of NPN BJTs and another pair of PNPs. A load connects to the battery through a 50 mΩ current-sensing resistor. For a maximum load current of 10 A, the input voltage to the sensing circuit will be 0.5 V. The BJTs in each current mirror pair should be as closely matched as possible to prevent offsets in the output voltage. You may need trimming to ensure the voltage stays within the ADC’s input range to achieve that match.

Figure 4. This current-sensing circuit uses both NPN and BJT current mirrors.

For each of these applications, you should use dual BJTs, which are two dies assembled in a single package. The proximity of the two dies ensures that their temperature will be tracked almost identically. Furthermore, using matched devices harvested from the same wafer area minimizes the possibility of deviations in the manufacturing process that could cause major differences in electrical parameters. This means their parameters have almost identical values, ensuring almost perfectly symmetrical behavior. Matched pair transistors eliminate the requirement for costly trimming in current mirror and differential amplifier applications, and compared to standard double transistors, they ensure accurate base-emitter voltage and current gain matching and are also fully internally isolated.

Voltage and current sources

Stable voltage or current sources are key requirements for most electronic applications, and while many integrated solutions offer these functions, they can be expensive. Thankfully, you can still implement these functions quickly and inexpensively using discrete BJTs.

Voltage regulation

Switching regulators are widely used as power supplies, but linear regulation is still needed for applications to reduce electromagnetic interference (EMI) and voltage ripple. For example, when powering application-specific chips (ASICs), microcontrollers (MCU), application processors, and sensors. This is why linear regulators are often included after switching regulators in power supply blocks. Unlike switching regulators, the difference between input and output power is dissipated in a pass transistor such as a BJT, as shown in Figure 5. To minimize these power losses, linear regulators are mainly used in applications where the difference between input and output voltage is small or only small output currents are required. Figure 5 shows a basic linear regulator with feedback regulation where a PNP BJT drives the NPN pass transistor.

Figure 5. Basic linear regulators often use NPN BJTs to pass current to a load.

The minimum voltage drop across the BJT output stage is the sum of the emitter-collector saturation voltage of the PNP transistor and the voltage drop of the base-emitter junction of the NPN:

An error amplifier tracks output voltage using a resistor divider to regulate it. The error amplifier compares this feedback voltage to a reference voltage (VREF) and adjusts the PNP-BJT base drive accordingly, which in turn adjusts the drive of the pass transistor. In this way, if the feedback voltage exceeds the reference voltage, the error amplifier lowers the base current and vice versa.

Current stabilization

Loads such as an LED string can’t be directly connected to a constant voltage source — they require a stable current. This scenario arises because an LED’s forward voltage is temperature-dependent with a negative thermal coefficient. Thus, the current would continuously increase due to self-heating and/or increasing ambient temperature. This could eventually lead to thermal runaway, potentially destroying the LEDs in the string. Figure 6 shows how to implement a simple current sink using an NPN or a current source using a PNP BJT:

Figure 6. BJT-based current sink and source to produce a stable current and eliminate thermal runaway.

Here, the output current is given by:

Unfortunately, the stability of the output current is impacted by the negative temperature coefficient of VBE, which is approximately −2 mV/K, meaning the change in output current over temperature is:

You can partially compensate for this by using a PN or Zener diode to replace the ground-connected resistor in the base bias circuit. The benefit of using a Zener diode is that IOUT is independent of VCC, increasing its immunity to supply voltage ripple. Very precise current stabilization can be achieved by combining a BJT with a base drive controller (shunt regulator) to provide an accurate and thermally compensated control loop.

Extra insight through thermal models

Predicting the thermal behavior of discrete BJTs and their packaging is critical for some applications, and this is possible using Foster and Cauer RC models for thermal impedance.

The Foster model

The Foster thermal model of a BJT is derived by semi-empirically fitting a curve to Zth, resulting in the one-dimensional RC network shown in Figure 7. Note that a Foster model’s R and C values don’t correlate with actual locations on a physical device. The model parameters Ri and Ci are the thermal resistance and capacitance values used to create the thermal model for calculating the thermal impedance of a device. Manufacturers often provide thermal models for their BJTs that you can use to verify device behavior using software simulation tools.

Figure 7. Foster RC thermal model of a BJT.

The Cauer model

Figure 8. Cauer RC thermal model of a BJT where the ground symbol refers to ambient temperature.

The RC network also represents a Cauer model, but unlike the Foster model, thermal capacitances are connected to thermal ground (ambient temperature location) as shown in Figure 8, and they also have physical meaning, which allows them to be used in determining the temperature of internal layers within a semiconductor structure. An advantage of using the Cauer model is that it will enable the addition of external components to the device model, such as the thermal models for PCBs, heatsinks, etc., which is impossible using a Foster model.

Conclusion

While CMOS and wide bandgap semiconductor technologies have stolen the limelight, bipolar junction transistors remain unsung heroes in many electronic applications. They even outperform their more illustrious counterparts in some key applications. This article reviewed some of these use cases. It showed how advances in BJT technology ensure that these versatile devices are unlikely to disappear from the electronic landscape anytime soon.

Related EE World articles

When to use NPN and PNP transistors and FETs
What’s the difference between an IGBT and an IGCT?
Not to be forgotten: the simple, bipolar SCRs and TRIACs
Biasing bipolar transistor circuits
Dispelling Myths: Don’t believe it when they say you need a bipolar gate drive for eGaN FETs
FAQ on pull-up/pull-down resistors, Part 1

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Selection and implementation of BLDC control strategy https://www.powerelectronictips.com/selection-and-implementation-of-bldc-control-strategy/ https://www.powerelectronictips.com/selection-and-implementation-of-bldc-control-strategy/#respond Wed, 28 Aug 2024 09:41:12 +0000 https://www.powerelectronictips.com/?p=23294 By Shao Zhang, Qorvo Understanding the differences between trapezoidal, sinusoidal, and field-oriented control can help engineers understand the value of Field Oriented Control (FOC) and the choices available to optimize their designs. BLDC motors can be smaller, lighter, and quieter than traditional brushed DC motors while enhancing the reliability and energy efficiency of consumer, industrial, […]

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By Shao Zhang, Qorvo

Understanding the differences between trapezoidal, sinusoidal, and field-oriented control can help engineers understand the value of Field Oriented Control (FOC) and the choices available to optimize their designs.

BLDC motors can be smaller, lighter, and quieter than traditional brushed DC motors while enhancing the reliability and energy efficiency of consumer, industrial, automotive, and medical applications. Their brushless construction simplifies equipment design and maintenance by eliminating concerns like mechanical wear, conductive dust, audible noise, and electric arcing.

Control strategies ranging from basic trapezoidal control to smoother sinusoidal control and field-oriented control (FOC) let engineers choose various options to balance complexity and cost against performance and controllability.

Six-step or trapezoidal control

Sequentially energizing the three stator windings using a simplistic “on-off” excitation acts on the static magnetic field of the permanent magnet in the rotor, causing it to rotate. The cycle comprises six pulses applied to each winding to perform one revolution. The waveforms are relatively easy to generate and result in a trapezoidal back emf, as shown on the left of Figure 1. However, the force on the rotor is not purely in a tangential direction, which would be ideal to ensure continuous maximum torque. There is a periodic radial component as the motor rotates that reduces efficiency and causes wear, heating, and so-called “torque ripple.”

BLDC motor control strategies overview
Figure 1. Six-step and sinusoidal control of BLDC.

Sinusoidal and field-oriented control

Applying sinusoidal excitation can theoretically produce a smoothly rotating field that is always perpendicular to the field of the rotor magnet, resulting in consistent torque, as seen on the right of Figure 1. In practice, effects such as winding inductance and back EMF cause a phase shift in the resulting current and field that prevents simple sinusoidal control from delivering smooth and accurate control.

Field-oriented control (FOC) dynamically corrects the stator field amplitude and direction to achieve the torque and speed commanded by the application. The algorithm calculates the optimum winding current according to the instantaneous measured rotor position.

Field-oriented control to maximize torque

In principle, FOC controls the AC excitation current to keep the angle of the resulting field always perpendicular to the field of the rotor magnet. This produces the highest torque, eliminates torque ripple, maximizes efficiency, and minimizes mechanical wear by removing the radial load on the bearing.

The stator winding currents and consequent field intensity and direction can be represented as three rotating vectors 120 degrees apart in a common static frame. To minimize torque ripple and maximize efficiency, these currents, IU, IV, and IW, must be balanced such that their net sum is zero. FOC aims to achieve this balance, beginning by applying the ‘Clarke’ transformation. This simplifies the currents into two rotating vectors of amplitude and , 90 degrees apart in a static frame:

Converting these vectors into static components, ID (direct) and IQ (quadrature), in a rotating reference plane permits correlating them with the position of the rotor as it revolves. This is done using the ‘Park’ transformation:

θ is the rotor angle around the static and frame

Under steady-state conditions, ID and IQ are constant values and can be interpreted as the components of stator winding current that represent tangential and unwanted radial torque, respectively. FOC uses these values as inputs to feedback loops, typically using proportional-integral (PI) controllers that work to maximize IQ and minimize ID to zero. The resulting error amplifier outputs VD and VQ are passed through inverse Park and inverse Clarke transformations with subsequent pulse width modulation to drive a power stage, generating the three sinusoidal stator winding currents. The programmable gain values in a PI controller, Kp, and Ki, must be separately optimized for transient response and steady-state accuracy, respectively, and are heavily dependent on actual motor parameters, particularly winding resistance and inductance. However, advanced FOC controllers, such as those from Qorvo [1], have auto-tuning features where they ‘learn’ the characteristics of the connected motor. An outline of a BLDC motor controller using FOC is shown in Figure 2.

BLDC motor control strategies overview
Figure 2. FOC scheme for driving a BLDC motor.

Applications that benefit particularly from FOC are those where noise or vibration need to be minimized or where a low harmonic contact is desirable. In addition, FOC can enable an application to run at higher than nominal speed when required. This is achieved using ‘field weakening’ where the back-EMF is deliberately reduced by controlling the current ID to be lower to a negative value. This reduces the effective rotor magnetic field and allows higher speed, although torque is reduced.

Sensing rotor position and winding  currents

The rotor angular position must be known in FOC to resolve the Id and Iq components. The stator winding currents also need to be measured.

Several methods are available to detect the rotor position. Sensorless monitoring infers the position from the winding currents, back-emf, and a model of the motor characteristics. However, starting up under high load can be difficult and may require starting the motor with a trapezoidal drive. In this case, one winding is unenergized at any instant, and the zero crossings of the back-EMF present provide an accurate indication of the position. The application can then change to sine FOC when the motor is running.

Alternatively, using Hall sensors to detect the rotor position enables starting-up under high load conditions with precise torque control. A more expensive option is to use a magnetic resolver or an encoder with quadrature outputs, which provides highly accurate position measurements and can sense the direction of rotation.

Moreover, there are different ways to measure winding current. The most accurate method is to sample each of the three winding currents simultaneously using three sensing resistors, each connected to an ADC. The usual approach is to measure the inverter leg currents (Figure 3, left).

A single shunt resistor can be used for cost-sensitive applications, effectively measuring the DC-link current (Figure 3, right). Only one ADC is needed, and the phase currents are calculated using a single-shunt current reconstruction method. The timing of current sampling is crucial to capture an accurate average value. Accuracy can be impaired by effects such as ringing if the active vector duration is less than the minimum measurement period. Asymmetrical current sampling can overcome this but requires more complex calculations.

BLDC motor control strategies overview
Figure 3. BLDC motor current monitoring using three-shunt (left) and single-shunt (right) methods.

Implementing BLDC FOC

A complete motor-control application requires power management, analog sensing, PWM generation, gate-driving functions, and the processing core responsible for executing the FOC algorithm. System-on-chip devices optimized for motor control, such as the Arm® Cortex® based PAC5xxx series from Qorvo, integrate this circuitry in a single package. One variant in this family even integrates the power MOSFETs to directly drive low-power BLDC motors for applications such as hand-held devices and tools. These Power Application Controller® ICs support the approaches discussed in this article, including sensorless rotor position measurement or detection with Hall sensors or a quadrature encoder and single-shunt or three-shunt current sensing. They also allow hybrid trapezoidal/FOC mode for assured start-up and field weakening for operation above nominal speed.

Conclusion

Understanding the differences between trapezoidal, sinusoidal, and field-oriented control and the underlying operating principles can help engineers choose the right control strategy when developing BLDC motor applications. Field-oriented control can deliver accurate speed control with fast dynamic response and minimal torque ripple and can now be implemented using a single-chip control IC.

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