Murata has announced its extended product offering for the mobile and high-performance computing (HPC) markets with the launch of its latest silicon process technology to fabricate silicon capacitors with a density of 1.3µF/mm². The devices’ extremely low ESL and ESR support the highest performances of new power distribution networks (PDN) that require low impedance over a wide frequency bandwidth.

As digital ICs evolve to offer more features at lower voltages, resolving issues like noise and voltage fluctuation is critical. The solutions’ <40µm profile enables chip designers to embed the silicon capacitor into the package as close to the active die as possible to minimizing both the current path length and parasitic levels.

These multi-terminal devices satisfy the various SoC and microprocessor design requirements for multiple terminal capacitor networks. Replacing conventional monolithic ceramic capacitors with multi-terminal silicon devices reduces the total quantity of capacitors required on the board significantly, which improves the compactness of the end design. Fewer capacitors also result in savings in both bills of materials and mounting costs.