Soft switching in DC-DC converters reduces energy loss. SiC transistors allow for higher switching frequencies and, thus, smaller magnetics, which reduces heat.

Efficiency and power density are both essential factors in the design of power converters. Every contributor to energy loss generates heat that needs removal by costly and power-hungry cooling systems. The combination of soft switching and silicon carbide (SiC) technology increases switching frequencies, which can reduce the size and number of passive components that temporarily store energy and smooth the output of a switched-mode converter. SiC also provides the basis for converters that produce far less heat and take advantage of smaller heatsinks.

With traditional silicon power transistors, the transition to soft switching from simpler hard-switching architectures in power-converter design enabled improvements in efficiency and frequency. We can, though, go further by taking advantage of SiC technology. The change in process technology enables more effective applications of soft-switching.

The key difference between hard and soft switching is that soft switching reduces or eliminates loss contributions of the default voltage and current conditions during the turn-on and turn-off phases of power transistors. Figure 1 shows the contributions to losses that these different phases make.

Designers have employed zero voltage switched (ZVS) techniques with silicon technology to eliminate turn-on switching loss. The remaining dominant losses in power switches are conduction loss and turn-off switching loss. Simultaneous swings in voltage and current lead to sizeable losses as switching frequency increases. Conceptually, soft switching tunes the voltage and current timing swings to reduce or eliminate the losses. The term “soft switching” applies to numerous techniques that designers can use to limit losses.

Zero-voltage switching (ZVS) is the most widely used form of soft switching for the turn-on phase and adopts a simple core principle: reduce the voltage between the drain and source before current can flow freely through the transistor channel. Before turn-on, the output capacitance charges to the same level as V_DS. The output capacitance is the sum of the drain-source capacitance and the capacitance between the gate and drain. To enjoy the benefits of ZVS, this stored charge must discharge into the load to avoid losses caused by the fall in drain-source voltage and rise in drain-source current occurring at the same time during turn-on. Ideally, the current starts to rise while the voltage across the transistor channel is already low (near zero).

Other sources of loss

Though widespread use of ZVS addresses the most important source of loss in switching converters, there are other sources of loss that need careful attention for designers to take advantage of higher-frequency operation. Some applications in more traditional designs expose these inefficiencies. The demands of leading AI applications, such as large language models, have led to an increased need for accelerators that operate close to the thermal limit of IC packaging, with hundreds of watts delivered to each device on a PCB. That results in a dramatic rise in the electrical power needed to supply high-density racks that host multicore microprocessors, graphical processing units, and dedicated AI accelerators.

Power demands have reached the point where power converters supply as much as 8 kW to rackmount systems. In doing so, they will take energy from an AC or DC feed operating at several hundred volts and convert the voltage down to 48 V at high current levels for distribution to the individual processor complexes. That demands power converters combine high efficiency with high density. Converters also need to withstand faults that involve voltage surges of 600 V or more. Since ZVS soft-switching reduces the turn-on switching loss to near zero, the dominant loss in a power semiconductor becomes conduction loss in ZVS soft-switching applications. This places a focus on the next key cause of loss of efficiency: conduction losses caused by resistance in the transistor channel while current passes through.

Low resistance

Ideally, on-state resistance should be as low as possible in a power converter. Process improvements have helped silicon superjunction devices meet these needs. However, designers can now take advantage of wide bandgap technologies such as silicon carbide (SiC) to benefit from the lower resistance for applications with bus voltages in the 400V to 800V range.

A key advantage of SiC in high-density power converters is its ability to support high breakdown voltages with very low R_dsA (on-resistance per unit area), a key advantage for deployment in data centers where distribution voltages need to be high enough to prevent excessive resistance losses through the power cables.

SiC devices are not made equal. It is tempting to replace a silicon superjunction MOSFET with its nearest SiC equivalent to take advantage of the improvements in efficiency and power density. SiC-based designs present other opportunities that make it worthwhile exchanging the MOSFET structure for one that delivers large reductions in on-state resistance. The junction field-effect transistor (JFET) structure provides key advantages. It has a conceptually simpler structure, shown in the lower right of Figure 2. Thus, it delivers a lower overall resistance that benefits from carriers not having to pass from the source through a MOSFET-like channel before entering the n-type drift region that connects to the drain. This lets the on-resistance converge closer to the theoretical limit governed by breakdown voltage. This allows a JFET to deliver a high margin of safety on breakdown voltage compared to MOSFETs, while delivering lower on-state resistance per unit area.

One reason the JFET is less commonly used in power circuits is that it is a normally-on device that requires a negative voltage to turn off completely. A cascode structure leads to more MOSFET-like (normally off) control. This places the SiC JFET in series with a low-voltage silicon MOSFET. By using a low-voltage Si device in a cascode arrangement, as shown at the top-right of Figure 2, designers can minimize overall operating resistance. A balanced design leads to the MOSFET contributing less than 10% to the overall on-state resistance. It is possible to integrate both MOSFET and JFET in a single package to aid integration and design – this device type is a SiC FET, distinct from the SiC MOSFET.

By using the low-voltage Si MOSFET to split the control gate from the JFET, you avoid other tradeoffs that often reduce the performance of MOSFET-based designs. The decoupling of gate control makes it possible to optimize the gate voltage and its associated charge without sacrificing the performance of SiC. Standard SiC MOSFETs often require a high gate voltage. This often needs to be close to 20 V to guarantee correct operation across the full operating temperature range. The cascode architecture coupled to a JFET makes it possible to use lower gate voltages (0 V to 12 V). This helps reduce gate charge, another potential source of losses incurred during switching, especially for soft-switching applications with high switching frequency at light load.

Using a JFET and silicon MOSFET together in a cascode configuration provides further opportunities for improving efficiency through reductions in Miller capacitance (gate to drain capacitance, C_gd). High capacitance adversely affects the switching speed of MOSFETs. The improvements enabled by the cascode arrangement carry through into density because they make it possible to drive the switching frequency higher than is practical with conventional silicon devices.

Though ZVS avoids turn-on losses, there is still dead time during which there is no power delivery. This dead time, which can last as long as 300 ns for a silicon-based design, imposes a limit on the maximum usable switching frequency because it reduces the proportion of each cycle that can be used for the on-state. At a switching frequency of 500 kHz (2 µs period), a 300ns dead-time period on both turn-on and turn-off edges represents 30% of the on-cycle. The SiC JFET offers a 10x lower output capacitance compared to silicon superjunction MOSFETs, providing much reduced required dead time and increased frequency.

It is important not to neglect opportunities for loss reductions in the turn-off phase, which can be more advantageous when changing to SiC technology. If additional circuitry is not used when the transistor turns off, the current and drain-source voltage will change simultaneously. This will result in losses similar to those seen in hard switching during the turn-on phase. However, fast turn-off not only reduces turn-off switching loss but also introduces high turn-off voltage spikes and ringing on device drain-to-source terminals.

There are two popular ways to control turn-off drain-to-source voltage spikes and ringing. One is using high gate resistance (R_g) to slow down the device switching speed. The other is using low gate resistance with a drain-to-source RC snubber to dampen the V_DS spikes and ringing. A common misconception is that using a snubber is very inefficient. Using a snubber is more efficient than using high gate resistance for topologies such as LLC resonant or phase-shifted full bridges that often incorporate ZVS switching techniques.

In ZVS soft switching applications, the added drain-to-source snubber capacitor does not generate any turn-on loss. Additional snubber capacitance between the drain and source, combined with low gate resistance, provides a higher displacement current in the complementary freewheeling device during the turn-off dV/dt transition. This can further decrease the overlap between turn-off current and voltage, resulting in much-reduced turn-off switching loss compared to simply using high gate resistance. With this approach, we contain V_DS ringing without sacrificing device switching speed, which would be required if the high-gate resistance strategy were to be used. Figure 3 shows how using a snubber can reduce ringing.

A double pulse test conducted with an 800 V bus voltage and 100 A load current in Figure 4 shows that adding a snubber results in a 52% reduction in losses for an SiC MOSFET module. The combination of using JFET-based devices with a snubber delivers an additional 74% reduction in turn-off switching loss. This makes it possible to increase the switching rate threefold and drives a reduction in the size of external passive components. Citing the simulation of a 50 kW phase-shifted full bridge (PSFB), the 74% reduction in turn-off switching loss drives a 10% reduction in junction temperature. Ultimately, better thermal performance leads to smaller heatsinks and cooling structures; combined, the two translate into a reduction in converter volume.

Though soft switching has many intricacies, SiC technology provides an opportunity to optimize its use. Designs that need high efficiency and high density can achieve their targets by moving outside the confines of classic MOSFET-based structures.

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