Wide bandgap (WBG) semiconductor devices, such as Silicon Carbide (SiC) field-effect transistors (FETs), are renowned for their minimal static and dynamic losses. Beyond these attributes, this technology can endure high pulse currents, proving particularly advantageous in applications like solid-state circuit breakers. This article delves into the characteristics of SiC FETs, offering a comparative analysis against traditional silicon solutions.

The ongoing pursuit to minimize power losses in semiconductor switches is spearheaded by WBG devices, with SiC FETs taking center stage. These devices, constructed as cascodes of a SiC junction-gate field-effect transistor (JFET) and co-packaged silicon metal-oxide-semiconductor field-effect transistor (MOSFET), stand out as normally off devices with user-friendly gate drives. Their impressive portfolio of “figures of merit” outshines competing technologies, specifically focusing on on-resistance per unit die area (R_DSxA), a metric capturing the combination of low static and dynamic power losses with cost-effectiveness. Despite their smaller die size, which translates to more units per wafer and reduced device capacitances, SiC FETs defy expectations by exhibiting enhanced temperature tolerance and increased peak current capability. Let’s take a look at the numbers.

SiC FETs On-Resistance performance

Quantifying the performance of a SiC FET, exemplified by the 750V-rated device from Qorvo (part UJ4SC075005L8S in a TOLL package), reveals an R_DSxA figure 2.2 times better than Gen 4 SiC MOSFETs, consistently maintained across the entire temperature range. In practical terms, this device displays an on-resistance of 5.4 mΩ at 25 °C and 9.2 mΩ at 125 °C, surpassing silicon or SiC-MOSFETs and Gallium Nitride high-electron-mobility transistor (GaN HEMT) rated at 600/650 V in the same package by a factor of 4 to 10.

To leverage this ultra-low resistance for a high current rating, the sample SiC FET uses silver sinter die attach and advanced wafer-thinning techniques to achieve 0.1 °C/W thermal resistance from junction to case. Additionally, the maximum junction temperature for the SiC device is 175 °C, meaning a single device can continuously handle 80 A when attached to a simple 0.58 °C/W heatsink, with the junction at 175 °C in an 85 °C ambient setting.

SiC FETs peak current rating

The maximum junction temperature (T_J,Max) figure for a SiC device and its current rating are essentially dictated by the packaging used. Despite the intrinsic material capability of SiC to operate safely at temperatures exceeding 500 °C, the maximum is limited to 175 °C in the JFET of a cascode SiC FET. This restriction still allows SiC FETs to handle transient peak currents significantly higher than their continuous rating when initiated from lower temperatures. The transient thermal impedance plot for a specific die and package, such as the aforementioned SiC FET device, outlines these characteristics, as shown in Figure 1.

For instance, a single 100 µs pulse results in a transient increase in the junction temperature of about 0.015 °C per Watt of power dissipated. At approximately 10 ms pulse duration, the thermal impedance from junction to case approaches the steady-state value.

Practical implications for the sample SiC FET device are depicted in Figure 2 and Figure 3. In each scenario, the device case is soldered to a copper plane on a PCB with copper thermal vias through to a back-side aluminum heatsink held at 50 °C, separated by an insulating thermal interface material (TIM). Figure 2 illustrates that a thermal resistance of >1.2^oC/W from junction to ambient may be expected, while the die and TOLL package determine the transient thermal response below approximately 1 ms.   As depicted in Figure 3, with this arrangement, the continuous rating is 89 A, while the device can handle up to 588 A peak current for a 500 µs single pulse before reaching T_J,Max of 175 °C.

SiC FETs vs. Si-MOSFETs

While SiC FETs showcase impressive results, a crucial question arises: how do they compare to Si-MOSFETs, commonly used in lower-power solid-state circuit breakers? The current squared through time (I²t) rating, a familiar measure for devices handling surge current, provides a compelling comparison.  The sample SiC FETwithstands 588 A for 500 µs, while the Si-MOSFET rating stands at about 200 A, showcasing an ‘I2t’ difference of 8.6 times, as illustrated in Figure 4.

Additional benefits of high peak current rating

Beyond the evident safety margin provided by SiC FETs under overload conditions, there are further advantages. SiC FETs prove highly suitable for power conversion circuits with inductive loads, where voltage overshoot is expected. These devices exhibit robust avalanche capability and a 750V rating. Moreover, board-mounted DC-DC converters in servers and similar applications increasingly require a high peak power rating in a compact form factor, driven by data-intensive applications such as artificial intelligence (AI), machine learning (ML), and streaming.

Designs of these converters often assume that junction temperatures will approach their maximums due to peak currents experienced. Digital control, facilitated by sensors and prediction algorithms through PMBus, provides junction temperature feedback, instructing the load to throttle back” as needed to prevent the switch junctions from exceeding their absolute maximum. The ample margin provided by SiC FETs instills confidence in the reliability and lifetime of the power system, potentially reducing the need for multiple paralleled devices and resulting in cost and board area savings.

Solid-state circuit breakers, designed to respond to high fault currents, can use SiC FETs and JFETs for their low voltage drop, displacing insulated-gate bipolar transistors (IGBTs), especially at lower current levels. The peak current rating of SiC FETs adds robustness to these breakers, allowing over-current detection circuitry to incorporate a longer delay before reacting. This attribute makes the circuit breaker more immune to ‘nuisance’ triggering.

Conclusion

Compact SiC FETs with peak current ratings in the hundreds of amps emerge as ideal components for modern power conversion applications demanding high power density and peak load handling. Metrics affirm that these components outperform GaN and Si- or SiC-MOSFET parts in the same voltage class.

This article is part of our 2024 Power Electronics Handbook.

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For almost all electronic products and systems, high reliability should be expected. Still, in some markets, reliability cannot be compromised or a trade-off for other performance factors. In particular, mission-critical industrial and medical applications, which require almost constant use, are expected to provide reliable operation over many years. So, a fundamental design requirement is choosing underlying subsystems and modules that can deliver on this expectation.

In terms of overall reliability, power supplies are especially important. A failure of these critical assemblies means a complete system failure and downtime that, at best, can impact cost and, at worst, could literally be the difference between life and death. 

A wide range of high-voltage DC-DC power supplies are available including products that are optimized for industrial and medical applications.

In this article, we will look at some key factors to help ensure optimized reliability when choosing and designing-in precision DC-DC high-voltage power supplies.

High-voltage power solutions
In today’s competitive markets, reliability is vital. However, the cost of unexpected failure can be exceptionally high in specific mission-critical applications. Many applications that require high-voltage power fall into the “mission-critical” category. In the world of semiconductor manufacturers, for example, failure of a high-voltage power system used for plasma generation would be expensive in terms of system downtime and the need to scrap work in progress. The same is true in other industrial applications ranging from factory automation to glass manufacture. In the medical field, where high-voltage supplies have become a fundamental element of equipment used for monitoring, diagnosis, and treatment, the consequences of failure can range from misdiagnosis to serious patient harm or even death.

With the wide range of potential applications for high-voltage power supplies, it is no surprise that many types are available. These include everything from large multi-kilowatt rack-mount designs to lower power solutions with output voltages in the tens of kilovolts. In addition, there are smaller, modular supplies as well as PCB-mount DC-DC converters for delivering high voltage to the point of use.

Selecting high-voltage power supplies
While specifications are essential in selecting an appropriate solution for a given application, it is only part of the story. Equally important when considering reliability is an understanding of the design process behind the power supply and the margins employed during that process. Six of the most important areas to consider are:

Ideal operating range
Ensuring a power supply is used within its ideal operating range is important to maintain long life and reliability. Some suppliers will place restrictive caveats on these operational windows, while others design their solutions to operate indefinitely at their maximum voltage and current ratings. Achieving this requires careful planning of design margins. 

For example, critical components in the high-voltage section (such as capacitors, diodes, and magnetics) must be selected with ample voltage margin. Also, the geometry of traces on circuit boards must be able to carry more than the required current levels while keeping metal content to a minimum. Components with elevated levels of thermal dissipation need to be kept far away from temperature-sensitive components to reduce internal heating effects, which can affect temperature coefficient, stability, and overall product reliability.

Encapsulation & thermal considerations
Modern, compact, high-voltage DC-DC power supplies use some form of encapsulation to increase power supply reliability. Simply relying upon the physical spacing of high-voltage components in an open-air design drives up the size of the product to unmanageable scale. Over time, creepage paths will become compromised due to the inevitable ingress of dust, contaminants, and moisture. 

Therefore, selecting the right encapsulant is critical — and challenging. Suitable materials exhibit extremely high dielectric strength, but physical properties are also essential. Designers must choose materials with the highest combination of thermal conductivity and dielectric strength for their products. This ensures that these products will last through extended voltage breakdown resistance and long-term resistance to thermal degradation.

Power dissipation
The power dissipation of a typical high-voltage DC-DC supply is closely related to its power density. A supply designed to make it as compact as possible, using the best creepage path and encapsulation design principles, will have a small volume, which can be desirable in space-constrained applications. However, this can complicate thermal dissipation because there is less available surface area from which to extract heat. 

Additionally, care must be taken to ensure that components that dissipate relatively elevated heat levels (such as MOSFETs and driver amps) are physically located as close as possible to thermally conductive planes to allow heat to escape. This must be considered during the initial design phase of all products, including volume, footprint, and location of thermally active components. Achieving the ideal balance of size and thermal characteristics gives the user the smallest volume possible while ensuring long-term reliability.

Electrical connections
Using connectors and conductors that are properly sized for the applied voltage and the current level they must carry will also increase product lifespan and reliability. For low-voltage conductors, a comfortable margin is applied during the selection process to keep contact resistance to a minimum. This translates into less heat dissipation, which delivers higher reliability.

Conversely, if superior design principles are not applied, high-voltage output cables and connectors will be subjected to punishing attacks from ionization. The effects of ionization can become a serious reliability factor within the power supply. The most common contributors are sharp points and edges of trimmed component leads and poorly designed printed circuit board (PCB) circuit traces, which create high-voltage gradients. Over time, these gradients will break down the dielectric properties of even the best encapsulation compounds, cause “tracking” (PCB surface arcing), and lead to irreversible failure of the power supply. Techniques such as “ball soldering” can be applied to prevent these potential failures during the construction of the high-voltage sections. Unique to the high-voltage power supply industry, ball soldering increases reliability by eliminating sharp points and narrow edges on the PCB.

Robust product development based on time-proven construction techniques and the careful selection of high-voltage cables and interconnections will ensure long-term reliability by eliminating ionization-induced degradation.

Arc & short circuit protection
It is important to consider that arcing may occur outside the power supply – an unpleasant facet in nearly all high-voltage applications. With that in mind, designing a power supply to withstand arc occurrences is integral to the design cycle. This often means strategically placing arc-clamping components at all key connections, including but not limited to the DC input, I/O, and high-voltage return paths. After installation, these safeguards must be exhaustively evaluated by simulating arcing conditions at all expected intensity and frequency levels. This makes for a robust, reliable package that can be deployed in even the most demanding applications.

Design verification
After the initial design phases, products need thorough design verification testing. This step verifies that all the above design considerations will contribute to optimized reliability in the field. Once the power supply has passed this development phase, it is considered ready for manufacture.

Enhanced system reliability through power supply monitoring
Choosing a well-designed and optimized power supply helps mitigate potential reliability issues in the field. In addition, choosing the right power supplies can contribute to overall system reliability, as power supplies can help monitor overall system health and predict and prevent failures.

Abrupt failures rarely happen without any degradation or warning, provided you know where to look or listen. For example, a worn bearing in a fan or other mechanism will produce louder audible noise and may have more resistance to turning, which will increase motor current. A failing capacitor may lead to more ripple and noise on the supply line. 

Monitoring the power supply can detect these types of fault trends before failure or out-of-specification operation happens. One of the most significant advances in power supply intelligence is the Power Management Bus — or PMBus. 

This standard provides a means of controlling and monitoring a power supply through digital communications. Electrically compatible with an Inter-Integrated Circuit, or I2Cv(while offering more features and overcoming noise-related and other issues sometimes associated with the latter), PMBus, in conjunction with suitable software, allows for monitoring of the telltale signs of change that often occur before a failure. As a result, preventative maintenance can be implemented to minimize or eliminate potential system downtime.

Summary
High-voltage power is essential to many mission-critical systems where the consequences of failure are high. Selecting a suitable unit with sufficient margin for the application is a good starting point to reduce the risk of failure. Furthermore, understanding the design process in critical areas can also ensure longevity. In addition, intelligent power supplies incorporating technologies such as PMBus can support monitoring that provides insight into key aspects of the wider system, providing advance warning of degradation / impending failure and allowing for low-cost preventative maintenance.

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Andrea Gorgerino, EPC
GaN devices have gone from initial R&D to mainstream designs over the last 15 years. Unfortunately, there are many misunderstandings left-over from those early-stage developments or dead-end technology branches. One of the most pernicious is the topic of bipolar drive. In actuality, unipolar drives are the best way to drive eGaN FETs.

Bipolar gate drives are still used in power electronic circuits. But their applications are usually confined to high-voltage-class devices (≥ 1,200 V) and high-current circuits where layout limitations and component parameters create concerns for the cross-conduction effect called Miller effect.

The Miller effect appears in half-bridge topologies and happens when the complementary device (which is OFF) is subject to a high dV/dt generated by the device in the other half of the bridge turning ON. During this event, the capacitors of the OFF device are charged by the external dV/dt.

The current of interest charges the gate-drain capacitance, also known as Miller capacitance: This current then flows either through the gate resistor and then the gate driver (which attempts to keep the device OFF), or through the gate-source capacitance. In turn, the current flowing through gate-source capacitance will create a voltage from gate to source. If this voltage exceeds the device threshold voltage, the device begins to conduct some current. This current is a shoot-through current because it comes from the main bus capacitor and flows through both half-bridge devices. This shoot-through current leads to additional switching losses and could even lead to device failure if the voltage on the gate, and hence the current, is high enough.

Several strategies have been implemented in MOSFET designs to mitigate this effect at the circuit design level. In increasing order of complexity they are:
Minimizing gate loop parasitics in the layout allows the gate driver to bypass part of the current coming through the gate-drain capacitance.
Use of separate turn ON and OFF gate resistors allows the design to reduce the dV/dt while maintaining a strong gate driver to keep the OFF device OFF. This method is most effective when combined with item one above
Finally, a driver with an active Miller clamp can be utilized. This concept can be considered an expansion of item two above, where an additional turn-OFF pin is available on the driver. This additional OFF clamp is active after the turn-OFF event and further helps to clamp the gate during dV/dt events. But the driver must have the clamp built in.

It is possible to drive the gate to a negative voltage using a bipolar gate drive. In this way the current flowing through the gate-source capacitance now must charge the gate from a negative voltage, e.g. -5 V, instead of from 0 V. This approach provides additional headroom before the threshold voltage is reached. But the technique requires generating two separate voltages for each device, so it can add significant cost and complexity to the overall design.

The Miller charge ratio

Circuit-level mitigation strategies for the Miller shoot-through can add complexity and cost. Before committing to any such strategies, it is important to look at the impact of the device itself and its characteristics on this effect.

The most important parameter to consider is the Miller ratio which is defined as either a ratio of capacitances or a ratio of charges. Because semiconductor devices have quite non-linear capacitances versus voltage, we will use the Miller charge ratio which is more accurate. It is defined as Q_GD/Q_G(TH), where Q_G(TH) is the pre-threshold voltage gate charge. This criterion also automatically takes into consideration the effect of different threshold voltages, as lower thresholds imply lower Q_GS(TH).

It should be noted that in most datasheets Q_GD is given at 50% of the maximum V_DS of the device, while it is common to use FETs up to 80% of their rating. As an example, for an EPC2045 eGaN FET the difference in QGD from 50% to 80% voltage is about 10%.

Keeping the ratio as low as possible will minimize the voltage on the gate. More importantly, keeping the ratio below one will ensure the voltage on the gate will always stay below turn-on threshold. If this criterion can be met, we are guaranteed to avoid any shoot through.

Miller charge ratios for EPC eGaN FETs are all below one. This means eGaN FETs are not susceptible to Miller shoot through! For comparison, many 100-V and 200-V-class silicon MOSFETs are quite susceptible to Miller shoot-through and care should be taken when using such devices.

Another important consideration is threshold voltage variation with temperature. In silicon MOSFETs the threshold voltage falls with temperature. So when the device is at its operating temperature the Q_G(TH) can be as much as 50% lower than the datasheet value, which means a x2 factor on the Miller charge ratio. On the other hand, the variation for any eGaN FET is less than 10%.

By combining these two effects (gate-drain capacitance variation with voltage and threshold voltage variation with temperature) we can also see eGaN FETs are more stable than silicon MOSFETs regardless of Miller charge ratio calculated in nominal conditions.

In a nutshell, eGaN FETs don’t need bipolar drives. More specifically, bipolar drives should not be used because of reverse direction conduction in GaN FETs.

In a silicon MOSFET, a p-n junction forms a diode from the source to the drain of the transistor. Current flowing in the reverse direction (into the source) flows through this diode. This diode has the usual characteristics of a p-n diode such as a knee voltage around 0.7 V, and forward and reverse recovery.

In contrast, a GaN FET has no such diode. This quality is an advantage because it means Q_RR is zero. However, GaN FETs do conduct current in the reverse direction in a way like a diode. This reverse conduction path is formed by turning on the 2DEG in the reverse direction, using the positive gate‐drain voltage to enhance the channel. Therefore, if the gate voltage drops below 0 V, the reverse conduction voltage will rise by the same amount. Thus it is important not to use negative gate drive as to not increase this voltage drop.

This effect is only present during the dead-time interval, as when the gate is turned ON the GaN FET will conduct current with the same on resistance as in the forward direction. Although deadtime can be reduced thanks to the fast-switching characteristics of GaN devices, the additional losses when using a negative gate drive can still add up and are best avoided.

To illustrate the more severe loss due to a negative gate drive, consider a simple synchronous buck converter during deadtime conduction. We ignore the impact of negative drive on turn-OFF losses. The main conditions for the converter are:

700 kHz switching frequency
48 to 12 V, 10-A output
12 nsec deadtime
Turn-OFF V_GS = 0 V or -2 V

Results graphed in the nearby figure reveal the overall losses increase by 10% from 2.4 W to 2.6 W.

We have shown why the need for bipolar gate drive for GaN FET is truly a myth. Thanks to the low Miller charge ratios always below one, the induced shoot-through will not happen. And use of a negative gate drive can actually lead to more severe losses because of a larger voltage drop during deadtime.

At EPC, our reference designs and demo boards are designed with unipolar gate drive (0 V turn OFF), optimized layout, and if possible, separate Rg_ON and Rg_OFF. With these simple guidelines we can realize robust high performance.
References
EPC
J. Strydom, D. Reusch, S. Colino and A. Nakata, “AN003: Using Enhancement Mode GaN-on-Si Power FETs,” EPC, 2017. [Online].
R. Schnell, Analog Devices, 2018. [Online].
A. Lidow, M. de Rooij, J. Strydom, D. Resuch and J. Glaser, GaN Transistors for Efficient Power Conversion, Wiley, 2020.

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