The 100 V OptiMOS 5 Linear FET 2 is available in a TO-leadless package (TOLL) and offers a 12 times higher SOA at 54 V at 10 ms and 3.5 times higher SOA at 100 µs compared to a standard OptiMOS 5 with similar R _DS(on). The latter improvement is particularly important for the battery protection performed inside the battery management system (BMS) in case of a short circuit event. During such events, the current distribution between parallel MOSFETs is critical for the system design and reliability. The OptiMOS 5 Linear FET 2 features an optimized transfer characteristic that allows for improved current sharing. Taking into account the wide SOA and improved current sharing, the number of components can be reduced by up to 60 percent in designs where the number of components is determined by the short-circuit current requirement. This enables high power density, efficiency, and reliability for battery protection which is used in a wide range of applications including power tools, e-bikes, e-scooters, forklifts, battery backup units, and battery-powered vehicles.

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Reverse recovery at the system Level:

A SiC MOSFET integrated with a soft-body diode increases a converter circuit’s operating frequency and efficiency while decreasing the number of components.

Figure 1 shows a full bridge topology of a single-phase two-level converter and a pulse pattern that will cause a reverse recovery event. At t₀, all switches start in the off state. S₁ and S₄ are initially turned on during t_1, letting the current pass through the load. During t₂, S₄ returns to the off-state. The current must then change to the freewheeling path, which utilizes the body diode in S₂. This time is known as dead time, and the current will decay due to the path resistance. During the transition period between t₂ and t₃, S₄ turns back on, causing a shoot-through scenario that forces the body diode of S₂ to undergo reverse recovery. After the recovery instant, the parasitic inductance in the current path results in a voltage overshoot to maintain the current in the path.

Reverse recovery and softness factor

A snappy or reverse recovery occurs when a SiC diode transitions from “forward-conduction” to an “off-state.” To simplify the reverse recovery event, Figure 2 shows a diode’s ideal recovery current and voltage waveform (Fig. 2a) and a non-ideal current waveform for a MOSFET (Fig. 2b).

Fig. 2a shows two regions of time based on I_diode. From t₀ to t_{1, the reverse voltage VR (dashed line) application} forces the current to drop at a constant rate, dI/dt. During this period, the rate at which dI/dt changes is determined mainly by the applied V_R, circuit elements such as the complementary device’s external R_G, and parasitic circuit inductance. At the start of t_{1, excess carriers are removed from the drift region, and a depletion region begins to form, which build}s the voltage across the diode. The voltage reaches its target value V_R when I_rrm is met at t_{2, and there is no additional bias from the voltage source VR that increases} the current magnitude further. From t₂ to t_3, the voltage overshoots its target value as the parasitic inductance opposes the decreasing loop current, eventually settling at V_R. The voltage overshoot peak depends on the circuit’s parasitic inductance and rate of change of recovery current dI_r/dt_(max).

Typically, we use two formulas to evaluate the softness factor of a recovery event. Below is S1, a single-parameter ratio:

where t_a = t_2­– t₁ and t_b = t₃ – t₂.

When S₁ = 1, the time it takes for the current to reach Irrm equals the time it takes to return to 0 A or leakage values.

A second method of measuring the softness of a reverse recovery event is defined in the equation below:

Where: dI/dt is the current at the initial zero-crossing of the commuting current, and dI_r/dt_(max) is the max return current during t_b.

When S₂ = 1, the current flow rate into and out of the body diode is equivalent. Most devices never achieve an ideal S₁ and S₂ value. A snappy recovery will occur when S1 and S2 are less than 1, while a value greater than 1 is considered a soft recovery.

Figure 3 shows a half-bridge test circuit used to perform reverse recovery characterization. Like the pulse pattern described in Figure 1, the high-side device will initially switch on and off to allow a controlled amount of current to conduct through the body diode of the low-side MOSFET. The high-side device then turns back on, forcing the freewheeling current to commutate, overshoot, and eventually settle, completing the reverse recovery event. Test boards and other external circuitry should limit the influence on body diode characterization. Do your best to minimize the test board’s stray inductance in accordance with good PCB layout practice and ensure that the external circuitry is not limiting the switching capabilities of the MOSFET. Minimizing the area of the power and gate loops will reduce inductance and achieve greater switching control.

Managing reverse recovery and EMI

Temperature dependence is the major factor for V_DS overshoot and peak I_DS values during the reverse recovery event. Tests performed at high temperatures will provide “worst-case scenario” results. The free-wheeling current through the body diode slowly dissipates over time as heat. This heat causes a temperature change in the junction, decreasing the conductive path’s resistance and thus increasing the initial dI/dt.

Figure 4a shows the temperature dependence of the reverse recovery current. The test parameters include an R_G(ext) = 5 Ω, V_DS = 800 V, and I_D = 40 A. Increasing external gate resistance is recommended to achieve softer recovery characteristics such as reduced Q_rr, I_rrm, and dampened ringing. Improvements in reverse recovery obtained from increasing R_G(ext) are shown in Figure 4b). Higher gate resistance reduces the risk of snappy reverse recovery and can increase switching losses due to increased t_rr if overly dampened. Figure 4b) shows the reverse recovery current plotted versus time for various external R_G values. The reduced ringing effect in the current waveform will reduce unwanted EMI.

Table 1 demonstrates that increasing R_G will decrease dI/dt and Q_rr and dampen the initial oscillatory peak current level. In contrast, increasing R_G also increases t_rr, creating a tradeoff between overshoot and switching times. Always visually inspect the waveform  after measuring it.

Impact of reverse recovery on voltage and energy

You must also consider reverse recovery effects on voltage to ensure a power circuit won’t exceed the device’s safe operating area (SOA). Parasitic inductance in the commutating current path causes an overshoot in the voltage waveform. If ignored, you will violate SOAs and reduce the system efficiency and lifetime of the semiconductor device.

Figure 5a shows the I_SD recovery waveform of the low-side device as a function of time at T = 125°C and V_DS = 800 V. Figure 5b shows the V_DS recovery waveform as a function of time and Figure 5c shows the peak V_DS value as a function of external gate resistance. The devices tested are in a half-bridge configuration with 4 dies in parallel per switch position. As expected, the V_DS peak decreases as R_G(ext) increases. An R_G(ext) >3 Ω is required to remain within the device’s SOA.

Conclusion

The circuits shown help you mitigate overshoot voltage and unwanted EMI during the reverse recovery of a SiC MOSFET body diode. Reverse recovery is an inherent occurrence in MOSFET body diodes, and negative effects are amplified by increased junction temperature. Board or module circuit parasitics create oscillatory voltage spikes that can break device SOA limitations. You should accurately characterize the softness factor of a MOSFET body diode to understand the benefits gained from mitigation techniques fully. Increasing external gate resistance is the most common method for softening recovery characteristics and managing V_DS overshoot.

References

1993. J. B. Mohit Bhatnagar, “Comparison of 6H-SiC, 3C-SiC, and Si for Power Devices,” IEEE Transactions on Electronic Devices, vol. 40, no. 3, pp. 645-655, 1993.Singh R., S. Ryu, J.W. Palmour, A.R. Hefner. J. Lai, “1500 V, 4 Amp 4H-Sic JBS Diodes,” in International Symposium on Power Semiconductor Devices, Toulouse, 2000.
Romero, A., “Capacitance Ratio and Parasitic Turn-on,” Wolfspeed Inc., Durham, 2023.
Yuan, X., S. Walder and N. Oswald, “EMI Generation Characteristics of SiC and Si Diodes: Influence of Reverse-Recovery Characteristics,” IEEE Transactions of Power Electronics, vol. 30, no. 3, pp. 1131-1136, 2015.

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Vishay Intertechnology, Inc. introduced two new IGBT and MOSFET drivers in the compact, high isolation stretched SO-6 package. Delivering high peak output currents of 3 A and 4 A, respectively, the Vishay Semiconductors VOFD341A and VOFD343A offer high operating temperatures to +125 °C and low propagation delay of 200 ns maximum.

Consisting of an AlGaAs LED optically coupled to an integrated circuit with a power output stage, the optocouplers released today are intended for solar inverters and microinverters; AC and brushless DC industrial motor control inverters; and inverter stages for AC/DC conversion in UPS. The devices are ideally suited for directly driving IGBTs with ratings up to 1200 V / 100 A.

The high operating temperature of the VOFD341A and VOFD343A provides a higher temperature safety margin for more compact designs, while their high peak output current allows for faster switching by eliminating the need for an additional driver stage. The devices’ low propagation delay minimizes switching losses while facilitating more precise PWM regulation.

The optocouplers’ high isolation package enables high working voltages up to 1.140 V, which allows for high voltage inverter stages while still maintaining enough voltage safety margin. The RoHS-compliant devices offer high noise immunity of 50 kV/µs, which prevents fail functions in fast switching power stages.

Samples and production quantities of the VOFD341A and VOFD343A are available now, with lead times of six weeks.

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